1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a synchronous semiconductor device having a delay locked loop (DLL) for latency control.
2. Description of the Related Art
In general, a synchronous semiconductor device, such as a double data rate synchronous dynamic random access memory DDR SDRAM), outputs data according to a delay locked loop (DLL) and column address strobe (CAS) latency in a read operation. The CAS latency indicates the number of clock cycles until first data is output through a data pad from a read command synchronized with an external clock.
FIG. 1 is a block diagram illustrating a conventional synchronous semiconductor device.
Referring to FIG. 1, a synchronous semiconductor device 100 includes a clock buffer unit 110 for buffering an external clock CLK, a delay locked loop (DLL) 120 for determining a first delay time tD1 for delay-locking a source clock ICLK buffered by the clock buffer unit 110 and generating a delay locked clock DLLCLK by delaying the source clock ICLK by the first delay time tD1, a latency shifting control unit 130 for generating a shifting control signal CLSHIFT based on CAS latency CL, a command buffer unit 140 for buffering an external command CMD, an internal command generation unit 150 for generating an internal command ICMD2 in response to a source command ICMD buffered by the command buffer unit 140, a first variable delay unit 160 for delaying the internal command ICMD2 by the first delay time tD1 in response to a delay adjustment signal DLY_CTRL output from the delay locked loop 120, a latency shifting unit 170 for shifting an internal command CMDD delayed by the first variable delay unit 160 in response to the shifting control signal CLSHIFT and the delay locked clock DLLCLK, and an output unit 180 for outputting read data RD_DATA to an exterior in response to a read command RD_CMD shifted by the latency shifting unit 170.
The delay locked loop 120 includes a second variable delay section 121 for outputting the delay locked clock DLLCLK by delaying the source clock ICLK by the first delay time tD1 in response to the delay adjustment signal DLY_CTRL, a first replica delay section 123 for outputting a feedback clock FBCLK by delaying the delay locked clock DLLCLK by a second delay time tD2, a phase comparison section 125 for comparing the phase of the feedback clock FBCLK with the phase of the source clock ICLK, and a delay adjustment section 127 for generating the delay adjustment signal DLY_CTRL in response to an output signal PD of the phase comparison section 125. The second delay time tD2 is obtained by modeling a delay time generated on an internal input/output path, and includes a third delay time tD3 generated in the clock buffer unit 110 and a fourth delay time tD4 generated in the output unit 180.
The latency shifting control unit 130 includes a third variable delay section 131 for delaying a counting source signal CNT by the first delay time tD1 in response to the delay adjustment signal DLY_CTRL, a second replica delay section 133 for delaying a delayed signal DLYCNT1 output from the third variable delay section 131 by the second delay time tD2, a counting section 135 for counting a delay time tD1+tD2 of a delayed signal DLYCNT2 feeding back from the second replica delay section 133 with respect to the counting source signal CNT, and a shifting control section 137 for outputting the shifting control signal CLSHIFT corresponding to a result obtained by subtracting a counting signal NTCK1 output from the counting section 135 from the CAS latency CL.
Hereinafter, the operation of the synchronous semiconductor device 100 configured as above will be described with reference to FIGS. 2A and 2B.
FIG. 2A is a timing chart for explaining the operation of the synchronous semiconductor device 100 in a low frequency environment, and FIG. 2B is a timing chart for explaining the operation of the synchronous semiconductor device 100 in a high frequency environment.
Referring to FIG. 2A, the clock buffer unit 110 buffers the external clock CLK to output the source clock ICLK. At this time, the third delay time tD3 is generated by the clock buffer unit 110. The delay locked loop 120 delays the source clock ICLK by the first delay time till required for delay-locking and generates the delay locked clock DLLCLK.
Meanwhile, the counting section 135 counts the delay time tD1+tD2 of the delayed signal DLYCNT2 feeding back from the second replica delay section 133 with respect to the counting source signal CNT, and outputs a counting signal NTCK1 corresponding to a result of the counting, and the shifting control section 137 provides the latency shifting unit 170 with the shifting control signal CLSHIFT corresponding to the result obtained by subtracting the counting signal NTCK1 output from the counting section 135 from the CAS latency CL.
In such a state, when the external command CMD is applied from an exterior, the command buffer unit 140 buffers the external command CMD to output the source command ICMD. At this time, the third delay time tD3 is generated by the command buffer unit 140. Then, the internal command generation unit 150 generates the internal command ICMD2 corresponding to the source command ICMD. At this time, a fifth delay time tD5 is generated by the internal command generation unit 150. Subsequently, the first variable delay unit 160 delays the internal command ICMD2 by the first delay time tD1 based on a delay amount adjusted based on the delay adjustment signal DLY_CTRL, and outputs a delayed internal command CMDD. The latency shifting unit 170 shifts the internal command CMDD delayed by the first variable delay unit 160 in response to the shifting control signal CLSHIFT, wherein the latency shifting unit 170 shifts the internal command CMDD in synchronization with the delay locked clock DLLCLK.
Accordingly, the output unit 180 outputs the read data RD_DATA externally in response to the read command RD_CMD output from the latency shifting unit 170.
However, the synchronous semiconductor device 100 configured as above has the following concerns.
The latency shifting unit 170 shifts the delayed internal command CMDD in synchronization with the delay locked clock DLLCLK. However, the delayed internal command CMDD causes delay corresponding to the fifth delay time tD5 as compared with the delay locked clock DLLCLK. This is because the internal command generation unit 150 is further provided on an internal command path as compared with an internal clock path. Therefore a margin of the delayed internal command CMDD for being aligned in the delay locked clock DLLCLK is reduced, and is further reduced in the high frequency environment as illustrated in FIG. 2B.